
2010-2012 Microchip Technology Inc.
DS41417B-page 171
PIC16(L)F722A/723A
FIGURE 17-13:
I2C SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS)
SDA
SCL
SSP
IF
BF
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
7
8
9
P
1
0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
A8
R/W
=
1
AC
K
AC
K
R/W
=
0
ACK
R
e
cei
ve
F
irst
B
yte
of
A
ddress
Cle
a
re
d
in
so
ftwa
re
B
u
sM
aster
sends
S
top
co
n
d
itio
n
A9
6
R
e
ce
iv
e
S
e
cond
B
yte
of
A
d
dr
ess
C
lear
ed
b
yhard
w
are
w
hen
S
P
A
D
is
updat
ed
w
ith
lo
w
byt
e
of
a
ddre
ss.
UA
Clo
ck
is
h
e
ld
lo
w
u
n
til
update
of
S
P
A
D
h
a
s
ta
ke
n
pl
ace
UA
is
set
indicat
in
g
tha
t
the
S
P
A
D
need
sto
be
upda
ted
U
A
is
set
indi
cati
ng
that
S
P
A
DD
need
sto
be
updat
ed
C
le
ar
ed
by
har
dw
are
w
h
en
SSP
ADD
is
u
p
d
at
e
d
with
h
ig
h
by
te
o
fad
d
res
s.
SS
PBUF
is
wr
itte
n
with
con
tent
sof
S
P
S
R
D
u
m
yre
ad
of
S
P
B
U
F
to
cle
a
rB
F
flag
R
e
cei
ve
F
irst
B
yte
of
A
ddr
ess
1
2
3
4
5
7
8
9
D7
D6
D5
D4
D3
D1
AC
K
D2
6
T
ran
smitting
Dat
a
B
yte
D0
Du
m
yr
ea
d
o
fS
SPB
UF
to
cl
ea
r
B
F
flag
Sr
Cle
ar
e
d
in
so
ftwa
re
W
rit
eo
fSSP
BUF
Cl
ea
re
din
so
ftwa
re
C
o
m
p
le
tion
of
clea
rs
B
F
flag
CK
P
C
KP
is
se
tin
so
ftwa
re
,in
itia
te
str
a
n
sm
issi
on
C
K
P
is
au
tomat
ica
lly
cl
eare
d
in
har
dw
ar
e
hol
di
ng
S
C
Ll
o
w
Clo
ck
is
h
eld
lo
w
u
n
til
up
date
of
S
P
A
D
h
a
s
ta
ken
p
la
ce
da
ta
tran
smi
ssi
on
Clo
ck
is
h
e
ld
lo
w
un
til
CK
P
is
set
to
‘1
’
B
u
sM
a
ster
se
nds
Rest
ar
ts
co
ndi
tion
D
u
m
yr
ead
o
fS
S
P
B
U
F
to
clear
B
F
flag